1. Field of the Invention
The present invention relates to Flash memory, and more particularly to the reading of logical data from a Flash memory.
2. Description of Related Art
Single-bit serial and multiple-bit serial Flash memory has become popular due to low pin count and simplicity of the interface. The simplest interface is the one-bit Serial Peripheral Interface (“SPI”). The one-bit SPI protocol involves sending a 8-bit command, address bytes, and optional dummy bytes by a user to the SPI Flash memory device, and in response the SPI Flash memory device returns data to the user. A unique 8-bit command may identify a read, an erase/program, or another appropriate operation. Multiple-bit serial interfaces such as SPI-Dual, SPI-Quad, and the Quad Peripheral Interface (“QPI”) have been developed for high performance system applications which require fast read performance. In the SPI-Quad interface, an 8-bit command is provided serially one bit at a time, but all subsequent fields (e.g. address, optional dummy bytes, and data) are done on a 4-bit (Quad) serial basis to improve read thru-put. In the QPI interface, all of the fields (e.g. 8-bit command, address, optional dummy bytes, and data) are done in 4-bit serial. As such, the QPI interface provides an 8-bit command in two clock cycles, whereas the SPI-Quad needs eight clock cycles. Various multiple-bit serial Flash interface protocols are described in, for example, U.S. Pat. No. 7,558,900 issued Jul. 7, 2009 to Jigour et al.
Read operations by Flash memory typically include memory array read and logic read types. FIG. 1 is a schematic block diagram of circuits used in a typical Flash memory for performing a logic read. Logic 12 receives logic data such as status data and JEDEC manufacturer and part identification data from various registers 4. The logic 12 also receives serial input SI, which contains commands and various input data. The logic 12 fully decodes each command on the eighth clock, selects JEDECID, SR1 data or SR2 data if the command is a JEDEC, RDSR1 or RDSR2 command respectively, and provides the selected logic data as LOGICDATA to data register DataReg 14. The DataReg 14 also receives a data input ARRAYDATA from the memory cell array when the command is a memory read command. Based on input signals JEDEC, RDSR1 and RDSR2 from logic 12, the DataReg 14 selects either the logic data LOGICDATA or the array data ARRAYDATA and outputs the selected data as serial data out signal SDOUT/. A pad serial output circuit PadSO 16 includes an output driver which outputs SDOUT to a contact such as a lead, pad or pin of the packaged Flash memory device when enabled by either signal RDLD when SDOUT is logic data, and by signal OEIN when SDOUT is memory array data. The PadSO 16 is clocked by the system clock SCK, but the logic 12 and the DataReg 14 are clocked by clock signal CLK, which is the SCK clock buffered by PadSCK 10.
The logic 12 is shown in greater detail in FIG. 2. The logic 12 decodes commands in the serial input SI and provides a signal which uniquely identifies logic read commands, illustratively signal JEDEC for a JEDECID read command, signal RDSR1 for a status register one read command, and signal RDSR2 for a status register two read command. These signals are combined in combinational logic 24 to obtain the signal RDLD indicative of a logic data read command. Signal RDLD is applied to the select input of multiplexer 26, which selects LOGICDATA from one of its data inputs when the signal RDLD is asserted, and otherwise selects data from register 25, which stores memory array data received from the main array sense amplifiers 2.
PadSO 16 is shown in greater detail in FIG. 3. Output driver 34 is controlled by an output enable signal OE from D-type flip-flop 32, and clocked by CLK. The D-type flip-flop generates OE based on signal RDLD applied to the SET input and signal OEIN applied to the D input. Input OEIN is used for an array read. The D-type flip-flop 32 and the output driver 34 are both clocked by CLK.